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| Name | Last modified | Size | Description |
|---|---|---|---|---|
| Parent Directory | - | ||
| Addierer_parallel_seriell.pdf | 2021-09-10 15:53 | 620K | |
| Halbaddierer_Volladdierer.pdf | 2021-09-10 15:53 | 471K | |
| Logikgatter_und_JK-FlipFlop.pdf | 2021-09-10 15:53 | 342K | |
| Schieberegister.pdf | 2021-09-10 15:53 | 315K | |
| 4-bit-Paralleladdierer.jpg | 2021-09-10 15:53 | 315K | |
| 4-Bit-Parallel_ADD_SUB.pdf | 2021-09-10 15:53 | 302K | |
| Serieller_Addierer.pdf | 2021-09-10 15:53 | 289K | |
| Volladdierer.pdf | 2021-09-10 15:53 | 268K | |
| Serieller_4-Bit-Addierer_Beispiel.pdf | 2021-09-10 15:53 | 246K | |
| addierer.jpg | 2021-09-10 15:53 | 228K | |
| serieller_4-bit-Addierer_1.jpg | 2021-09-10 15:53 | 123K | |
| serieller_4-bit-Addierer_2.jpg | 2021-09-10 15:53 | 122K | |
| 4-Bit-Dualzähler_Triggerung_steigende_Taktflanke.jpg | 2021-09-10 15:53 | 55K | |
| serieller_4-bit-addierer_final.dsim | 2021-09-10 15:53 | 22K | |